System-on-chips (SoCs) have multiple power domains and reset domains. When a particular partition of a SoC is powered up but not reset, the logic in that partition will be in an unpredictable random state. To operate in a secure environment, it is necessary to start the operation from a known state and not a random state.
Some power-on-reset (POR) circuits or logic have been attempted to provide protection. However, these attempts rely heavily on analog characteristics to generate the duration of a reset pulse as well as the time when the reset pulse is asserted. This makes the logic susceptible to attacks where an attacker can control the slew-rate of the power supply and thus either cause the reset pulse to be generated too early during the power ramp-up or by ensuring a very short duration of the reset pulse which cannot propagate through the logic to effectively reset the chip.
Other attempted solutions rely on sequential elements (e.g. counters) containing a well-defined value (‘0’) upon power up to generate a POR pulse. Thus, these solutions are susceptible to the very attack they are trying to mitigate while implementing the POR Circuit. There have also been attempts to design POR circuits where reset remains asserted until a specific voltage threshold is reached. However, such circuits are susceptible to attacks with a fast ramp-up rate if the threshold to de-assert reset is low. Also, if the threshold to de-assert reset is too low, this can cause reset de-assertion even before logic is truly powered up. If the threshold voltage to de-assert reset is increased, this can result in erroneous resets during dynamic voltage and frequency scaling (DVFS).